1. Field of the Invention
The present invention relates to an apparatus for generating a substrate voltage in a semiconductor device, and more particularly to an apparatus for controlling a substrate voltage in a semiconductor device capable of obtaining an accurate circuit operation in a manner that a substrate voltage is maintained constant regardless of an unstable variation of a power supply voltage applied from an external source so as to prevent a threshold voltage variation and an operation point variation in a device.
2. Description of the Prior Art
In order to improve the performance of a DRAM, a negative substrate voltage V.sub.BB is necessary, for which in some cases in the past, a negative voltage was applied from an external source. However, it requires an additional power supply, resulting in that a power supply unit became complicated.
FIG. 1 is a block diagram showing a conventional substrate voltage circuit for avoiding any necessity of the external power supply, which includes a substrate 103; a substrate voltage detector 100 for outputting a signal to control a substrate voltage applied to the substrate 103; an oscillator 101 for being oscillated in response to the signal inputted from the substrate voltage detector 100; and a substrate voltage generator 102 for generating a substrate voltage in accordance with the output signal of the oscillator 101 and supplying it to the substrate 103.
The substrate voltage applied to the substrate 103 is generated as the oscillator 100 and the substrate voltage generator 102 are sequentially controlled by the substrate voltage detector 100.
FIG. 2 is a circuit diagram of the substrate voltage detector 100 with a relationship to adjacent circuits of FIG. 1, which includes a PMOS transistor 104 having a source to which a power supply voltage Vcc is applied, and with its gate connected to ground; an NMOS transistor 105 having its drain connected to the drain of the PMOS transistor 104 and having its gate connected to ground; a voltage dropping unit 106 being connected to the source of the NMOS transistor 105 for decreasing an output signal level of the source of the NMOS transistor 105 to a predetermined voltage level and applying the output signal to a substrate voltage terminal (not shown); a PMOS transistor 107 having a source to which the power supply voltage Vcc is applied and having its drain connected to the drain of the PMOS transistor 104; an inverter 108 having an output terminal to which a gate of the PMOS transistor 107 is connected, for inverting the signal commonly outputted from the respective drains of the PMOS transistors 104 and 107; the oscillator 101 being oscillated in response to a control signal from the inverter 108; and the substrate voltage generator 102 for generating a substrate voltage upon receipt of the output signal of the oscillator 101 and applying the generated substrate voltage to the substrate.
The voltage dropping unit 106 has an NMOS transistor 109 with the signal outputted from the source of the NMOS transistor 105 being commonly applied to the gate and to the drain thereof and applying the output voltage thereof to the substrate voltage terminal (not shown).
The operation of the conventional regulator as constructed above will now be described.
When the power supply voltage Vcc is applied to the source of the PMOS transistor 104, the PMOS transistor 104 is turned on while the NMOS transistor 105 is turned off, so that a voltage V.sub.OUT appears at a node N.sub.D without any drop) of voltage and accordingly the potential at the node N.sub.D becomes a high potential.
When the voltage of high potential at the node N.sub.D is applied to an input terminal of the inverter 108, the inverter 108 inverts it to output a low potential voltage.
When the low potential voltage outputted from the inverter 108 is applied to the oscillator 101, the oscillator 101 is oscillated and the voltage generator 102 is controlled by the output signal of the oscillator 101, to output a negative substrate voltage.
When the negative substrate voltage V.sub.BB is applied to the substrate 103 of FIG. 1, a potential difference between the gate and the source of the NMOS transistor 105 is increased over a threshold voltage, so that the NMOS transistor 105 is operated to be turned on.
Accordingly, a current path, namely, a discharge loop, is formed between the substrate and the node N.sub.D.
Immediately when the current path is formed, discharging occurs from the node N.sub.D to the substrate, so that the potential at the node N.sub.D is changed from a high potential to a low potential.
Accordingly, the low potential signal at the node N.sub.D is applied to the input terminal of the inverter 108 and the inverted output becomes a high potential.
The high potential signal, that is, the output inverted by the inverter 108, acts as a control signal to stop the operation of the oscillator 101, so that the operation of the substrate voltage generator 102 is stopped and the substrate voltage is not supplied any longer.
However, in the operation of the DRAM, when a voltage difference between the substrate voltage and the gate of the NMOS transistor 105 is reduced below a threshold voltage as the substrate voltage is increased due to several factors, the NMOS transistor 105 is turned off, so that the voltage V.sub.OUT at the node N.sub.D is converted to a high potential according to the power supply voltage, and then this high potential voltage is again converted to a low potential voltage by the inverter 108. Thus, the oscillator 101 and the substrate voltage generator 102 are operated again so as to generate an originally stable substrate voltage.
Accordingly, the increased substrate voltage is changed to an originally stable substrate voltage value to thereby stabilize the operation of the semiconductor device.
The PMOS transistor 107 is adapted for use as a hysteresis control loop and prevents a malfunction of the oscillator 101 and the substrate voltage generator 102 in a transient state, at the very moment that a voltage level outputted from the inverter 108 is converted.
The operation of the substrate voltage detector of the semiconductor device will now be described by equations.
When the substrate voltage detector 100 is operated and a substrate voltage at a normal level is generated, the PMOS transistor 104 and the NMOS transistor 105 are operated at their saturation region.
Accordingly, the source-drain current I.sub.DSP of the PMOS transistor 104 is expressed by equation (1) below, while the source-drain current I.sub.DSN of the NMOS transistor 105 is expressed by equation (2) below where Vss equals about 0 volts. EQU I.sub.DSP =K.sub.P (V.sub.cc -V.sub.TP).sup.2 ( 1) EQU I.sub.DSN =K.sub.N (v.sub.BB +V.sub.TN).sup.2 ( 2)
V.sub.TP and V.sub.TN are threshold voltages of the PMOS transistor 104 and the NMOS transistor 105, respectively, and K.sub.P and K.sub.N are constants of the PMOS transistor 104 and the NMOS transistor 105, respectively.
From the equations (1) and (2), since the values of I.sub.DSP and I.sub.DSN are the same to each other, the equation (3) below is obtained for the substrate voltage V.sub.BD. ##EQU1##
Therefore, the substrate voltage is considered to be proportional to the power supply voltage. In this respect, it should be noted that the substrate voltage is linearly proportional to the power supply voltage as shown in FIG. 4.
An optimal substrate voltage should be maintained at a constant value as shown by the dotted line in FIG. 4, even though the power supply voltage is increased.
However, the regulator having the above construction of the PMOS transistor 104 and the NMOS transistor 105 as described above has a problem in that the substrate voltage is linearly increased as the power supply voltage is increased as shown in equation (3). Thus, the variation of the substrate voltage renders the threshold voltage of each device to be varied and also varies the operational point of a circuit, causing a disadvantage that an accurate circuit operation as desired can not be obtained.